1. Field of the Disclosure
The present disclosure generally relates to the field of integrated circuits having an internal circuitry and a protection circuit to minimize the risk of damage due to electrostatic discharge (ESD) events.
2. Description of the Related Art
In modern integrated circuits usually a very large number of individual circuit elements, such as field effect transistors, capacitors, resistors and the like are formed on a small substrate area to provide the required functionality of the circuitry. Typically, a number of contact pads are provided, which, in turn, are electrically connected to respective terminals, also referred to as pins, to allow the circuitry to communicate with the environment to provide the required input/output (I/O) capabilities. As feature sizes of the circuit elements are steadily shrinking to increase packing density and enhance performance of the integrated circuit, the ability for withstanding an externally applied over-voltage to any of the pins of the integrated circuit decreases significantly. One reason for this resides in the fact that decreasing feature sizes of field effect transistors, which is a dominant design component of complex circuitry based on CMOS technology, i.e., reducing the channel length of the field effect transistor, typically also requires scaling down the thickness of the insulation layer separating the gate electrode from the channel region in order to maintain controllability of a channel that forms at the gate insulation layer upon application of an appropriate control voltage to the gate electrode. Any over-voltage supplied to the thin gate insulation layer, however, will lead to defects in the gate insulation layer, resulting in reduced reliability, or to destruction, possibly resulting in a complete failure of the integrated circuit.
One major source of such over-voltages are so-called electrostatic discharge (ESD) events, wherein an object carrying charges is brought into contact with one or more of the pins of the integrated circuit. For example, a person can develop very high static voltage from a few hundred to several thousand volts, merely by moving across a carpet, so that an integrated circuit may be damaged when the person contacts the integrated circuit, for example, by removing the integrated circuit from the corresponding circuit board. A corresponding over-voltage caused by an ESD event may even occur during the manufacturing of the integrated circuit and may thus lead to a reduced product yield. Moreover, nowadays there is an increasing tendency to use replaceable integrated circuits in electronic systems so that only one or more integrated circuits have to be replaced instead of the whole circuit board in order to, for example, upgrade microprocessors and memory cards. Since the re-installation or replacement of integrated circuits is not necessarily carried out by a skilled person in an ESD-safe environment, the integrated circuits have to be provided with corresponding ESD protection. To this end, a number of protective circuits have been proposed that are typically arranged between a terminal of the integrated circuit and the internal circuit to provide a current path ensuring that the voltage applied to the internal circuit remains well below a specified critical limit. For example, in a typical ESD event caused by a charge carrying person, a voltage of several thousand volts is discharged in a time interval of about 100 ns (nanoseconds) or less, thereby creating a current of several amperes. Thus, the ESD protection circuit must allow a current flow of at least several amperes to ensure that the voltage across the ESD protection circuit does not exceed the critical limit.
A plurality of ESD protection circuits have been developed which basically attempt to provide appropriately designed current paths in order to discharge excess charge without damaging the sensitive circuit components of functional blocks in the integrated circuit. For example, a relatively straightforward approach is frequently used, in which each of the input/output terminals may be associated with a dedicated protection circuit, for instance in the form of diodes to enable a current flow between a respective pair of input/output terminals, across which an undesired high voltage may occur during an ESD event. Respective approaches may be referred to as pad-based ESD protection. Hence, in this case, a solid ESD current path has to be provided, which may provide the required current drive capability in both possible current flow directions. In CMOS technology, for this purpose, frequently NMOS transistor elements may be used with several configurations, such as gate grounded NMOS transistors, gate coupled NMOS transistors and the like. Typically, the NMOS transistor element may be operated during an ESD event by using the parasitic bipolar transistor, which, however, may, in sophisticated CMOS technologies, require significant efforts in obtaining sufficient current drive capabilities of the respective parasitic components. Therefore, the design of appropriate ESD protection circuits using the pad-based approach may be less flexible with respect to portability to different manufacturing technologies.
In another strategy, the excess charge created by an ESD event may be supplied to the supply voltage power rail and may then be shorted to the ground via an appropriately designed power clamp circuit, which may be provided in the form of an appropriately designed transistor element. Since the power clamp must not be enabled during normal operational conditions, for instance during power up and continuous operation, a trigger circuit may be required to appropriately activate the power clamp upon occurrence of an ESD event, while avoiding the activation of the power clamp in other cases. Although this approach, frequently referred to as rail-based ESD protection, may include more complex circuitry and may involve a high current path via a first ESD protection element connecting a respective input/output terminal with the VDD power rail and subsequently connecting the power rail to the ground rail via the power clamp circuit, this technique is less dependent on technology-specific characteristics and may therefore provide a higher degree of flexibility during technology changes. For this reason, the rail-based ESD protection technique may be frequently employed in complex CMOS technology. However, although significant advantages with respect to design flexibility and independence of technological characteristics may be provided by the rail-based approach, in certain approaches, the high probability of creating erroneous trigger situations may occur, which will be explained in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates an integrated circuit 100 comprising a typical rail-based protection circuitry which may include a primary ESD protection circuit 110, for instance, provided in the form of a high current diode structure, as previously explained. The primary ESD circuit 110 may thus be directly connected to an input/output pad 103, which may be connected to an output stage 104 of a functional block 105 of the integrated circuit 100, which has to be protected with respect to high voltage pulses, such as ESD events. Thus, the primary ESD circuit 110 may typically be designed so as to restrict a voltage at the input/output pad 103 to a tolerable value during certain ESD events. Furthermore, a secondary ESD circuit 120 may be connected to an input stage 106 of the internal circuit 105 and may be coupled to the input/output pad 103 via a resistive structure 111. Hence, the secondary ESD circuit 120 may be essential in protecting the highly sensitive input stage 106, which may comprise advanced transistor elements having extremely sophisticated gate dielectrics, as previously discussed. Furthermore, the integrated circuit 100 typically comprises a first power rail 101, which may receive the supply voltage VDD during normal operation of the device 100. Similarly, a second power rail 102 is provided, i.e., a power rail for connecting the ground potential or “negative” supply voltage VSS to the circuit 100. Additionally, the circuit 100 comprises a further ESD protection circuit 130 including a trigger circuit 140 and a power clamp circuit 150. For example, the power clamp circuit 150 may be provided in the form of a high current N-channel field effect transistor having the required current drive capability for accommodating the high current flow created during an ESD event. The trigger circuit 140 comprises a trigger stage 160, which may comprise a resistor 161 and a capacitor 162, which may commonly define an RC time constant. Furthermore, the trigger circuit 140 comprises a first inverter stage 170, a second inverter stage 180 and a third inverter stage 190, connected in series between the trigger stage 160 and a control input 151 of the power clamp transistor 150.
During normal operation, the supply voltage may be applied across the first and second power rails 101 and 102, thereby resulting in the supply voltage occurring at the input node of the first inverter stage 170 after the settling time of the RC trigger stage 160. That is, if the RC time constant of the trigger stage 160 is significantly less than the rise time of the supply voltage upon powering up the circuit 100, the voltage at the input of the inverter stage 170 may rise substantially in the same manner as the slowly rising supply voltage at the power rail 101. Due to the chain of the inverter stages 170, 180, 190, the output of the last inverter stage 190, and thus the control gate 151 of the power clamp transistor 150, may remain in a low state, thereby avoiding a shorting of the power rails 101, 102.
FIG. 1b schematically illustrates the circuit 100 during the occurrence of an ESD event. It may be assumed that a high voltage signal, such as a contact with a human body and the like, may result in the creation of excess charge at the input/output pad 103. As previously indicated, a respective ESD pulse may have significantly shorter rise times in the order of approximately some tens of nanoseconds, which may be comparable to the RC time constant of the trigger stage 160. Thus, during the occurrence of the ESD event, the primary and secondary ESD circuits 110, 120 may become conductive and may connect the pad 103 to the power rail 101, thereby creating an increase of voltage across the power rails 101 and 102. Due to the relatively short rise time that may be comparable to the RC time constant of the trigger stage 160, the voltage at the input of the inverter stage 170 may remain at a relatively low level, while the “supply voltage” may rise in a fast manner according to the rise time of the ESD pulse. Consequently, the output of the first inverter stage 170 may turn into a high state, that is, it may follow the rising voltage VDD, thereby also resulting in a high state at the control gate 151 of the power clamp transistor 150, which may therefore be turned on, thereby providing a conductive path between the power rails 101 and 102 for discharging the excess charge transferred to the input/output pad 103. Hence, the voltage at the input/output 103 may be maintained at a non-critical value, while also maintaining the voltage drop across the power rails 101, 102 at a non-critical value. Thus, upon appropriately dimensioning the RC time constant of the trigger stage 160, an appropriate trigger behavior of the ESD protection circuit 130 may be accomplished, in which it may be distinguished between a normal power up situation and the occurrence of a fast pulse, as is typically the case in ESD situations. However, in complex CMOS designs, resistors may typically be provided in the form of field effect transistors so as to save valuable semiconductor area in the chip. In this case, the trigger behavior of the circuit 160 may differ from the operational behavior described above for the following reasons.
FIG. 1c schematically illustrates the trigger circuit 160 in the conventional arrangement as described above on the left-hand side and the corresponding arrangement of the trigger circuit 160 in accordance with a design in which the resistor 161 is replaced by a P-channel transistor 163. Furthermore, as illustrated, the capacitor 162 may be provided in the form of the parasitic capacitance, i.e., the gate/drain and the gate/source capacitance of a field effect transistor 164. For this purpose, the transistor 163 is typically designed so as to exhibit a corresponding resistance to obtain, in combination with the parasitic capacitance of the transistor 164, the required RC time constant. However, due to the fact that the transistor 163 may become conductive only after exceeding the threshold voltage, which may be dependent on the overall design of the transistor 163, the actual RC time constant may be significantly higher at an initial phase upon applying voltage to the power rail 101. Hence, in this situation, the RC time constant of the trigger stage 160 as shown on the right-hand side may become comparable to the rise time of a power up situation, since the transistor 163 may not be conductive at all when the input voltage is below the threshold voltage, which may finally result in an incorrect triggering of the power clamp transistor 150. Thus, during power up events of the device 100, a significant current may be drawn by the power clamp transistor 150, which may significantly reduce overall performance of the device 100 in view of settling time and overall power consumption, while also requiring an increase current drive capability of a power source for supplying the circuit 100.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.